MicroTCA (short for Micro Telecommunications Computing Architecture, also: μTCA) is a modular, open standard, created and maintained by the PCI Industrial Computer Manufacturers Group (PICMG). It provides the electrical, mechanical, thermal and management specifications to create a switched fabric computer system, using Advanced Mezzanine Cards (AMC), connected directly to a backplane. MicroTCA is a descendant of the AdvancedTCA standard. == History == The rapid expansion of mobile telecommunications and their associated services (such as text messages) at the beginning of the millennium increased the demand of processing power in telecommunication systems. The existing "carrier grade" (see RAS) computing architectures were not fit to house the high performance processors of the time. In order to answer those demands, about 100 companies worked together in PICMG, resulting in the Advanced Telecommunications Architecture (AdvancedTCA, ATCA), published in 2002. After the introduction of AdvancedTCA, a standard was developed, to cater towards smaller telecommunications systems at the edge of the network. This standard was geared towards a more compact, less expensive systems, without cutting back on reliability or data throughput. This standard, called MicroTCA, was ratified 2006. MicroTCA systems migrated after its release into non-telecommunication sectors, like defence, avionics and science. This resulted in extensions to the base-standard, called modules. == Modules == === MicroTCA.0 === The base-specification for properties common to all other modules, ratified July 6, 2006. This includes: Mechanical specifications, like possible dimensions of card cages, backplanes and supported AMC-modules Electrical specifications, like power distribution and interface layout Thermal specifications, like possible cooling layouts or available cooling power Management specifications A second revision of the base-specifications was ratified January 16, 2020, containing some corrections, as well as alterations, necessary to implement higher speed Ethernet fabrics, like 10GBASE-KR and 40GBASE-KR4. === MicroTCA.1 === This module adds specifications for ruggedized systems, using forced air for cooling. Possible scenarios for MicroTCA.1-based systems include outside plant telecom, industrial and aerospace environments === MicroTCA.2 === This module adds specifications for more stringent requirements with regards to temperature, shock, vibration and other environmental conditions. These specifications are geared towards use in outside plant telecom, machine and transport industry, as well as military airborne, shipboard and ground mobile equipment. MicroTCA.2 allows the use of air- and conduction-cooled AMC-modules. === MicroTCA.3 === This module adds specifications for even more stringent requirements with regards to temperature, shock, vibration and other environmental conditions. These specifications are geared towards use in outside plant telecom, machine and transport industry, as well as military airborne, shipboard and ground mobile equipment. MicroTCA.3 requires the use of conduction-cooled AMC-modules. === MicroTCA.4 === This module extends the AMC with a Rear Transition Module (RTM), increasing PCB-space and modularity. AMC and RTM are connected with a connector, located in zone 3, defined in MicroTCA.0. These specifications are geared towards use in large-scale scientific devices, like particle accelerators or telescopes. == Components of MicroTCA == === Card Cage === The card cage (also: shelf, crate) houses all the other components and as such has two primary functions: Provide mechanical stability to the other components Ensure sufficient cooling There exist a wide array of card cages. They usually differ in: the type of modules they support (MTCA.0, MTCA.1, ...) the number of slots they provide (typically between 2 and 12) the architecture of the installed backplane (see below) the cooling scheme they use (i.e. airflow front-to-back, bottom-to-top, side-to-side, conductive,...) === Backplane === The backplane is a printed circuit board, mounted directly into the card cage. It connects all other components of a MicroTCA system to each other and provides power, data access and management access to them. Two types of power are distributed over the backplane, Management Power (+3.3 V) and Payload Power (+12 V). Unlike typical backplanes, where power is distributed to all components via a common "powerplane" in the PCB, on a MicroTCA backplane, Management and Payload Power are distributed to each component individually. While Management Power is provided to each module connected to a powered backplane, Payload Power has to be granted by the MicroTCA Carrier Hub (MCH), after ensuring that the module is MicroTCA-compatible. The standard defines various communication buses, which the backplane can/should provide: Gigabit Ethernet IPMI SATA Fat pipe (can be used for PCIe, SRIO or 10G/40G Ethernet) Point to Point Links Clocks JTAG === Cooling Unit === The Cooling Unit (CU) provides controlled air flow in air-flow-cooled card cages. It usually consists of an array of fans and a controller, which is connected to the backplane. The MicroTCA Carrier Hub (MCH) can read-out temperature sensors (if present) and fan speed, as well as change fan speed via IPMI. The Cooling Unit is usually fitted to a specific card cage. Some CUs are easily detachable (i.e. for cleaning or replacement), while other card cages come with integrated, non-detachable CUs. === Power Module === The Power Module (PM, also: Power Supply) converts the AC power from the power line to the +3.3 V Management Power (MP) and +12 V Payload Power (PP), both of which are DC. There exist a variety of power modules, which differ in: form factor (i.e. double width, single width) input voltage (110 V, 220 V, both) output power (i.e. 600 W, 1000 W) The power module senses the presence of a module in a slot via a specified pin in the module connector, and immediately provides that module with management power. Payload power is managed by the MicroTCA Carrier Hub (MCH), which communicates with the power module via IPMI. The power module uses its own type of connector, and can thus only be installed into designated slots, which in turn can't carry any other type of module. Some card cages provide an additional power module slot for redundancy. In such a case, one slot is the primary, which will provide power by default, and the other one is secondary, providing power only, if the primary does not. === MicroTCA Carrier Hub === The MicroTCA Carrier Hub (MCH) is the central managing device of a MicroTCA card cage. It manages power distribution and cooling. It usually also provides Gigabit Ethernet and/or PCIe/Serial RapidIO switching. Some MCHs additionally provide clocking. As the name indicates, they are the hub of various star topologies (i.e. for Ethernet, PCIe) on the backplane and thus require dedicated slot(s). Some backplanes support two MCHs for redundancy. In this case there are two MCH slots, with one being designated primary, and one secondary. === Advanced Mezzanine Card === Advanced Mezzanine Card (AMC) is a standard for hot-pluggable PCBs. It was originally developed to be used in AdvancedTCA systems. The standard specifies: the dimensions of the PCB with two width variants (single, double) and three height variants (Compact, Mid-size, Full) type, location and orientation of connectors (i.e. Zone 1, 2, 3) There is a huge variation of functionalities, an AMC can fulfill: Computing (i.e. a module with CPU, RAM, SSD and on-board graphics) Storage (i.e. SSD carrier) Graphics card FPGA card (i.e. for signal processing) FMC carrier Digitizer card (Analog-Digital and Digital-Analog Conversion) Clocking and Triggering and others === Rear Transition Module (MTCA.4 only) === The Rear Transition Module (RTM) was added in the MicroTCA.4 standard. It is connected directly to an AMC via a connector, located in zone 3, requiring a double width AMC and RTM. An RTM has about the same dimensions, as an AMC, basically doubling the available PCB-space per slot in an MTCA.4 card cage. Its power is provided by the AMC. Thus an RTM can not operate on its own, but requires a paired AMC. The zone 3 connector is electrically free configurable, making it possible, that a mechanically fitting AMC-RTM pair is electrically incompatible. To avoid damage due to that incompatibility, a mechanical code-pin was added to MTCA.4-compatible AMCs and RTMs, mechanically preventing the installation of an electrically incompatible RTM to an AMC. The functionality of RTMs includes, but is not limited to: RF-signal pre-/post-processing (i.e. filtering, Up-/Down-conversion, Vector De-/Modulation) Digital signal pre-/post-processing Clock-generation/-distribution Device interfaces Date storage CPU (only MCH-RTM)
Distinguishable interfaces
Distinguishable interfaces use computer graphic principles to automatically generate easily distinguishable appearance for computer data. Although the desktop metaphor revolutionized user interfaces, there is evidence that a spatial layout alone does little to help in locating files and other data; distinguishable appearance is also required. Studies have shown that average users have considerable difficulty finding files on their personal computers, even ones that they created the same day. Search engines do not always help, since it has been found that users often know of the existence of a file without being able to specify relevant search terms. On the contrary, people appear to incrementally search for files using some form of context. Recently researchers and web developers have argued that the problem is the lack of distinguishable appearance: in the traditional computer interface most objects and locations appear identical. This problem rarely occurs in the real world, where both objects and locations generally have easily distinguishable appearance. Discriminability was one of the recommendations in the ISO 9241-12 recommendation on presentation of information on visual displays (part of the overall report on Ergonomics of Human System Interaction), however it was assumed in that report that this would be achieved by manual design of graphical symbols. == VisualIDs, semanticons, and identicons == The mass availability of computer graphics supported the introduction of approaches that make better use of the brain's "visual hardware", by providing individual files and other abstract data with distinguishable appearance. This idea initially appeared in strictly academic VisualIDs and Semanticons works, but the web community has explored and rapidly adopted similar ideas, such as the Identicon. The VisualIDs project automatically generated icons for files or other data based on a hash of the data identifier, so the icons had no relation to the content or meaning of the data. It was argued not only that generating meaningful icons is unnecessary (their user study showed rapid learning of the arbitrary icons), but also that basing icons on content is actually incorrect ("contrasting visualization with visual identifiers"). The Semanticons project developed by Setlur et al. demonstrated an algorithm to create icons that reflect the content of files. In this work the name, location and content of a file are parsed and used to retrieve related image(s) from an image database. These are then processed using a Non-photorealistic rendering technique in order to generate graphical icons. Developer Don Park introduced the identicon library for making a visual icon from a hash of a data identifier. This initial public implementation has spawned a large number of implementations for various environments. In particular, identicons are now being used as default visual user identifiers (avatars) for several widely used systems. They are also used as a complement to Gravatars, which are pre-existing avatar images created or chosen by users, instead of automatically generated images. (see #External links). == Current research == While current web practice has followed the semantics-free approach of VisualIDs, recent research has followed the semantics-based approach of Semanticons. Examples include using data mining principles to automatically create "intelligent icons" that reflect the contents of files and creating icons for music files that reflect audio characteristics or affective content.
SERVQUAL
SERVQUAL is a research tool that measures customer perception of service quality by comparing what customers expect from a service to their assessment of the service actually delivered. The instrument was developed in the United States in the mid-1980s by researchers A. Parasuraman, Valarie Zeithaml, and Leonard L. Berry, and is designed for use in after-service evaluation processes. It assesses service quality across five dimensions: reliability, assurance, tangibles, empathy, and responsiveness. SERVQUAL has been applied in sectors including healthcare, banking, education, and libraries. == Overview == The SERVQUAL questionnaire consists of matched pairs of items, 22 expectation items and 22 perception items, organized into five dimensions that correspond to the consumer's mental framework for evaluating service quality. Each item is part of a pair: one question asks what excellent organizations in a given industry should offer (expectation), and the other asks how the specific organization being evaluated performs (perception). == The model of service quality == The model of service quality, referred to as the gaps model, was developed by Parasuraman, Zeithaml, and Berry during a systematic research program conducted in the 1980s. The model identifies five gaps that may cause customers to experience poor service quality. In this framework, gap 5 is the service quality gap, which represents the difference between customer expectations and their perceptions of the service. This is the only gap that can be directly measured, and the SERVQUAL instrument was designed specifically to capture it. Gaps 1 through 4 have diagnostic value and point to probable causes of service failures. == Development of the instrument == Development of the model of service quality began in 1983 and, after iterative refinements, led to the publication of the SERVQUAL instrument in 1988. The research team conducted in-depth interviews and focus groups in four service sectors: retail banking, credit card services, securities brokerage, and product repair and maintenance. The questionnaire was tested across multiple samples to verify its reliability, validity, and factor structure. == Adaptations and variants == SERVQUAL has been adapted for specific industries and contexts. Well‑known derivatives include: LibQUAL+ – a library service quality survey developed by the Association of Research Libraries. EDUQUAL – an instrument tailored for the evaluation of service quality in educational institutions. HEALTHQUAL – adapted for measuring patient perceptions of healthcare service quality. ARTSQUAL – used to evaluate visitor perceptions of quality in museums and performing arts venues. == Criticisms == Researchers have raised several concerns about SERVQUAL. Critics argue that the instrument's definition of expectations is ambiguous and that it does not adequately account for the dynamic nature of customer expectations over time. Other scholars question whether the five‑dimension structure is universally applicable across all service contexts, and whether a generic instrument can capture the unique attributes of specific industries without modification.
Fooocus
Fooocus is an open source generative artificial intelligence program that allows users to generate images from a text prompt. It uses Stable Diffusion XL as the base model for its image capabilities as well as a collection of default settings and prompts to make the image generation process more streamlined. == History == Fooocus was created by Lvmin Zhang, a doctoral student at Stanford University who previously studied at the Chinese University of Hong Kong and Soochow University. He is also the main author of ControlNet, which has been adopted by many other Stable Diffusion interfaces, such as AUTOMATIC1111 and ComfyUI. As of 9 July 2024, the project had 38.1k stars on GitHub. == Features == Fooocus' main feature is that it is easy to set up and does not require users to manually configure model parameters to achieve desirable results. According to the project, it uses GPT-2 to automatically add more detail to the user's prompts. It includes common extensions such LCM low-rank adaptation by default which allows for faster generation speed. Fooocus prefers a photographic style by default, with a list of predefined styles to choose from. While Fooocus aims to provide good results out of the box, it also includes an "advanced" tab that allows for user customization. The user interface is based on Gradio. It appears this project has not been updated in over 1 year. The latest git update for Fooocus was in Aug 12, 2024.
Leading the Future
Leading the Future is an American super PAC network focused on lobbying for policies friendly to the artificial intelligence industry. It was launched in 2025 with over $100 million from industry stakeholders including Andreessen Horowitz, OpenAI President Greg Brockman and Palantir co-founder Joe Lonsdale. The launch was preceded by talks between Collin McCune, head of government affairs at Andreessen Horowitz, and Chris Lehane, chief global affairs officer at OpenAI. Among the members of the network are the American Mission PAC, which supported Chris Gober, and the Think Big PAC, which targeted Alex Bores. Leading the Future is affiliated with the nonprofit Build American AI, which Axios describes as a dark money advocacy "offshoot" operating alongside the super PAC. NBC News states that the network’s efforts are modeled after the pro-cryptocurrency group Fairshake. Leading the Future is led by Zac Moffatt and Josh Vlasto, the latter of whom previously served as an advisor to Fairshake. In response to the creation of Leading the Future, former members of Congress Brad Carson and Chris Stewart co-founded the super PAC network Public First, aiming to counter the group’s influence. In April 2026, an investigation by Model Republic linked Leading the Future to The Wire By Acutus, an automated news website that allegedly used AI agents posing as human journalists to solicit interviews. The site's content was found to closely mirror the PAC's deregulatory policy goals while targeting researchers and advocates skeptical of rapid AI development. In May 2026, Wired revealed that Build American AI used a "dark money" campaign to pay TikTok and Instagram influencers $5,000 per video to promote scripted narratives framing Chinese AI as a "national security threat." According to internal documents and staff at the marketing agency managing the project, the campaign's explicit goal was to "subtly shift public debate" toward the deregulation of AI industries while intentionally avoiding technical discussions regarding AI quality or safety. During the 2026 primary season Leading the Future went on to endorse several candidates in both Democratic and Republican races with several of them going on to win.
Ampere Computing
Ampere Computing LLC is an American fabless semiconductor company that designs ARM-based central processing units (CPUs) with high core counts for use in cloud computing and data center environments. Founded in 2017 by former Intel president Renée James, the company is headquartered in Santa Clara, California, and operates as an independent subsidiary of SoftBank Group since November 2025. == History == Ampere Computing was founded in fall 2017 by Renée James, ex-President of Intel, with funding from The Carlyle Group. James acquired a team from MACOM Technology Solutions (formerly AppliedMicro) in addition to several industry hires to start the company. Ampere Computing is an ARM architecture licensee and develops its own server microprocessors. Ampere fabricates its products at TSMC. In April 2019, Ampere announced its second major investment round, including investment from Arm Holdings and Oracle Corporation. In June 2019, Nvidia announced a partnership with Ampere to bring support for Compute Unified Device Architecture (CUDA). In November 2019, Nvidia announced a reference design platform for graphics processing unit (GPU)-accelerated ARM-based servers including Ampere. In the first half of 2020, Ampere announced Ampere Altra, an 80-core processor, and Ampere Altra Max, a 128-core processor, without the use of simultaneous multithreading. In March 2020, the company announced a partnership with Oracle. In September 2020, Oracle said it would launch bare-metal and virtual machine instances in early 2021 based on Ampere Altra. In November 2020, Ampere was named one of the top 10 hottest semiconductor startups by CRN. In May 2021, the company announced a partnership with Microsoft. In April 2022, Ampere said that it had filed a confidential prospectus with the U.S. Securities and Exchange Commission, signaling its intent to go public. In June 2022, HPE announced their Gen11 ProLiant system would use Ampere Altra and Ampere Altra Max Cloud Native Processors. In July 2022, Google announced T2A instances using Ampere Altra in the Google cloud and in August 2022 Microsoft announced their instances of Ampere running in Azure. On March 19, 2025, investment holding company SoftBank Group announced it will acquire Ampere Computing for $6.5 billion. The deal finalized in November 2025, with Ampere remaining as an independent subsidiary with its headquarters in Santa Clara, California. == Products == Ampere develops ARM-based computer processors and CPU cores under their Altra brands. These are used in databases, media encoding, web services, network acceleration, mobile gaming, AI inference processing, and other applications and programs that need to scale. On February 5, 2018, Ampere announced the eMAG 8180 featuring 32x Skylark cores fabricated on TSMC's 16FF+ process. It supports a turbo of up to 3.3 GHz with a TDP of 125 W, 8ch 64-bit DDR4, up to 1 TB DDR4 per socket, and 42x PCIe 3.0 Lanes. The Skylark cores were based on AppliedMicro's X-Gene 3. Packet offers servers with the eMAG 8180 and 128 GB DRAM, 480 GB SSD, and 2x 10 Gbit/s networking. On September 19, 2018, Ampere announced the availability of a version featuring 16x Skylark cores. === 2020 === On March 3, 2020, Ampere announced the Ampere Altra featuring 80 cores fabricated on TSMC's N7 process for hyperscale computing. It was the first server-grade processor to include 80 cores and the Q80-30 conserves power by running at 161 W in use. The cores are semi-custom Arm Neoverse N1 cores with Ampere modifications. It supports a frequency of up to 3.3 GHz with TDP of 250 W, 8ch 72-bit DDR4, up to 4 TB DDR4-3200 per socket, 128x PCIe 4.0 Lanes, 1 MB L2 per core and 32 MB SLC. Ampere also announced their roadmap with Ampere Altra Max (2021) in development and AmpereOne (2022) defined. === 2021 === The 128-core Altra Max was released in 2021 and targeted hyperscale cloud providers. It uses the same server socket and platforms as Ampere Altra, and both products have one thread per core. The Altra Max CPUs provide 128 Arm v8.2+ cores per chip and run up to 3.0 GHz. They also support eight channels of DDR4-3200 memory and 128 lanes of PCIe Gen4. Also in 2021, Oracle launched its Oracle Cloud Infrastructure (OCI) using Ampere Altra processors. === 2022 === In February 2022, Ampere and Rigetti Computing announced a strategic partnership to create hybrid quantum-classical computers. The companies will combine Ampere's Altra Max CPUs with Rigetti's Quantum Processing Units (QPU) in cloud-based High-Performance Computing (HPC) environments. In April, Microsoft previewed its Azure Virtual Machines running on the Ampere Altra. The VMs run scale-out workloads, web servers, application servers, open source databases, cloud native .NET applications, Java applications, gaming servers, media servers, and other processes. In May, Ampere announced the sampling of AmpereOne CPUs, 5 nanometer chips based on its in-house Ampere-developed core. AmpereOne will add support for DDR5 main memory and PCIe Gen5 peripherals. On June 28, 2022, HPE became first tier-one server provider to offer compute with optimized cloud-native silicon for service providers and enterprises embracing cloud-native development with new line of HPE ProLiant RL Gen11 servers, using Ampere® Altra® and Ampere® Altra® Max processors, delivering high performance and power efficiency. === 2023 === During April 2023, Ampere released the Altra developer's kit, an IoT Prototype Kit based on Ampere Altra, aimed at cloud developers, available in 32-core, 64-core, and 80-core formats. === 2024 === In May 2024, Ampere updated its AmpereOne roadmap to 256 cores and announced a joint effort with Qualcomm on CPUs and accelerators. == Customers == Ampere's customers include Microsoft Azure, Tencent Cloud, Oracle, ByteDance, Hewlett Packard Enterprise (HPE), Cloudflare, Equinix, Kingsoft Cloud, Meituan, Scaleway, UCloud, Foxconn Industrial Internet, Gigabyte, Inspur, Cruise, Hetzner, Project Ronin, Wiwynn and Google Cloud Platform Cruise uses an Ampere Altra variant for its autonomous driving unit. The CPU was selected because of its throughput and low power consumption. In 2021, Oracle, Microsoft, Tencent, and ByteDance committed to using Ampere's customized chips, first announced in May. In April 2022, Microsoft previewed Ampere Altra processors in its new Azure D-and E- series virtual machines. The Dpsv5 series is built for Linux enterprise application types, and the Epsv5 series is for memory-intensive Linux workloads. They provide up to 64 vCPUs, include VM sizes with 2GiB, 4GiB, and 8GiB per vCPU memory configurations, up to 40 Gbit/s networking, and high-performance local SSD storage. In 2022, Microsoft's Ampere Altra-based Azure servers became the first cloud solution provider server to be Arm SystemReady SR certified. The Azure VMs, powered by Altra processors, were also the first to be SystemReady Virtual Environment standard certified. SystemReady defines a set of firmware and hardware standards as a baseline for system development for software developers, original equipment vendors, and chipmakers.
Cortica
Headquartered in Tel Aviv Cortica utilizes unsupervised learning methods to recognize and analyze digital images and video. The technology developed by the Cortica team is based on research of the function of the human brain. == Company Founding == Cortica was founded in 2007 by Igal Raichelgauz, Karina Odinaev and Yehoshua Zeevi. Together, the founders developed the company’s core technology while at Technion – Israel Institute of Technology. By combining discoveries in neuroscience with developments in computer programming, the team created technology that possesses the ability to interpret large amounts of visual data with increased accuracy. This technology, called Image2Text, is based on the founders’ work in digitally replicating cortical neural networks’ ability to identify complex patterns within massive quantities of ambiguous and noisy data. Cortica’s offerings have application in the automotive industry, media industries, as well as the smart city and medical industries. Industry experts suggest that the self-driving automotive industry alone will be worth upwards of $7 trillion while each connected car is expected to generate 4,000 GB of data per day. Beyond that, industry analysts expect the proliferation of surveillance cameras to continue leading to an expected 2,500 Petabytes of data being generated daily by new surveillance cameras. Cortica operates in these high scale industries. The company currently employs professionals from many domains including AI researchers as well as veterans of intelligence units within the Israeli Defense Forces. == Research and Technology == In 2006, Founders Raichelgauz, Odinaev, and Zeevi shared their findings with the 28th IEEE EMBS Annual International Conference in New York in a paper titled, “Natural Signal Classification by Neural Cliques and Phase-Locked Attractors”. That same year, the team also published “Cliques in Neural Ensembles as Perception Carriers" CB Insights recently identified Cortica as the number one patent holder among AI companies. Cortica is researching to develop a machine-learning driving system which can identify objects and pedestrians. Connecting to it, Elon Musk has been rumored to partner with Cortica for his electric car company, Tesla. However, Tesla denies it stating that Musk did not discuss a collaboration with artificial intelligence firm Cortica. == Funding == Cortica raised $7 million in its Series A funding round, announced in August 2012. Investors included Horizons Ventures (the investment firm of Hong Kong billionaire Li Ka-Shing), and Ynon Kreiz, the former chairman and CEO of the Endemol Group. In May 2013, it was announced that Cortica had raised $1.5 million from Russian firm Mail.ru Group. It later transpired that this was a part of Cortica's Series B funding round for $6.4 million, announced in June 2013. The round was led by Horizons Ventures, with participation from the Russian firm Mail.ru Group and other angel investors. In its fourth funding round, Cortica has raised $20 million, bringing the total investments to $38 million. According to a report from The Israeli lead Daily economic newspaper, TheMarker, the fourth round was led by a strategic Chinese investor who will probably help the company expand into the Asian market. == Media coverage == GigaOm listed Cortica as one of the top deep learning startups in a November 2013 article surveying the field, along with AlchemyAPI, Ersatz, and Semantria. Business Insider ranked Cortica as one of the coolest tech companies in Israel. CB Insights has identified Cortica as the top patent holding AI company. In 2017 several leading automotive media outlets covered the launch of Cortica's automotive business unit