Chris Callison-Burch is an American computer scientist and professor of computer and information science at the University of Pennsylvania (Penn), specializing in natural language processing (NLP), artificial intelligence (AI), and crowdsourcing. He is recognised for his contributions to machine translation, paraphrase generation, and the application of large language models (LLMs) to AI challenges, with over 200 publications cited more than 33,000 times. Callison-Burch has influenced public policy on AI and copyright, testifying before the U.S. Congress in 2023 on generative AI’s implications. He serves as the faculty director for Penn’s Online Master of Science in Engineering in AI program. == Education == Callison-Burch earned his PhD in Computer Science from the University of Edinburgh in 2008, focusing on machine translation and paraphrasing techniques. His doctoral research developed statistical methods for generating paraphrases in machine translation systems, laying the foundation for his later NLP work. Prior to his PhD, he studied at Stanford University, where he developed an interest in computational linguistics. == Career == After his PhD, Callison-Burch joined the Centre for Language and Speech Processing at Johns Hopkins University as a research faculty member from 2008 to 2013, working on NLP projects, including machine translation and crowdsourcing for creating training data. In 2013, he joined the University of Pennsylvania as an assistant professor in the Department of Computer and Information Science and was promoted to associate professor in 2017, and to full professor in 2024. At Penn, Callison-Burch teaches courses on AI and NLP, including CIS 5300 (Natural Language Processing) and CIS 5210 (Artificial Intelligence), which attract over 500 students annually. He directs Penn’s Online Master of Science in Engineering in AI program, launched in 2025. He teaches AI and NLP courses on Coursera, reaching thousands of global learners. Callison-Burch was a part-time visiting researcher at Google in 2019 and 2020, where he collaborated on applying Google's LLM to Dungeons & Dragons dialogues. In 2023, he took a sabbatical at the Allen Institute for AI (AI2), where he contributed to vision-language models. == Research == Callison-Burch’s research focuses on NLP, AI, and crowdsourcing, with significant contributions to machine translation, paraphrase generation, and LLMs for tasks like text simplification and bias detection. His early work developed crowdsourcing methods for machine translation, leveraging non-expert annotators for paraphrase-based evaluation, influencing platforms like Amazon Mechanical Turk. Recent projects have included several notable works. Molmo and PixMo (2025) are open-weight vision-language models developed with AI2, achieving state-of-the-art multimodal performance and earning a Best Paper Honourable Mention at CVPR 2025. Also in 2025, his work on Calibrating Large Language Models with Sample Consistency improves LLM reliability via sample-based calibration, presented at NAACL 2025. The Media Bias Detector (2025) is a real-time tool analysing selection and framing bias in news, using LLMs to detect persuasive language differences (e.g., Russian vs. English Wikipedia). Holodeck (2024) is a language-guided system for generating 3D embodied AI environments, presented at CVPR 2024. BORDIRLINES (2024) is a dataset for cross-lingual retrieval-augmented generation, focusing on culturally sensitive tasks. He has co-authored over 200 publications, featured at conferences like ACL, EMNLP, and CVPR. == Awards and recognition == Callison-Burch has received numerous awards: Best Paper Honourable Mention at CVPR 2025 for "Molmo and PixMo". Best Paper Award at the Workshop on Cognitive Modelling and Computational Linguistics (CMCL) 2024 for "Evaluating Vision-Language Models on Bistable Images". Best Paper Award at STARSEM 2016 for "So-Called Non-Subsective Adjectives". Best Paper Award at the Workshop on Sense, Concept and Entity Representations 2017 for "Word Sense Filtering Improves Embedding-Based Lexical Substitution". Honourable Mention Award at CHI 2018 for "A Data-Driven Analysis of Workers’ Earnings on Amazon Mechanical Turk". Google Faculty Research Award (2013) for crowdsourcing in NLP. Sloan Research Fellowship (2014). He has received research funding from Google, Microsoft, Amazon, Facebook, Roblox, DARPA, IARPA, and NSF. His h-index is 72, with over 33,000 citations. He served as General Chair of ACL 2017 and as the Program Co-Chair EMNLP 2015. == Public policy and testimony == On May 17, 2023, Callison-Burch testified before the U.S. House Subcommittee on Courts, Intellectual Property, and the Internet on AI and copyright law. His testimony emphasised generative AI’s role in creative industries and the need for balanced copyright frameworks. He has appeared on Fox News to discuss AI’s societal impact, and discussed its impact with other print news sources. He contributes to AI ethics discussions, including workshops on AI’s effects on writing and creative professions.
Highway network
In machine learning, the Highway Network was the first working very deep feedforward neural network with hundreds of layers, much deeper than previous neural networks. It uses skip connections modulated by learned gating mechanisms to regulate information flow, inspired by long short-term memory (LSTM) recurrent neural networks. The advantage of the Highway Network over other deep learning architectures is its ability to overcome or partially prevent the vanishing gradient problem, thus improving its optimization. Gating mechanisms are used to facilitate information flow across the many layers ("information highways"). Highway Networks have found use in text sequence labeling and speech recognition tasks. In 2014, the state of the art was training deep neural networks with 20 to 30 layers. Stacking too many layers led to a steep reduction in training accuracy, known as the "degradation" problem. In 2015, two techniques were developed to train such networks: the Highway Network (published in May), and the residual neural network, or ResNet (December). ResNet behaves like an open-gated Highway Net. == Model == The model has two gates in addition to the H ( W H , x ) {\displaystyle H(W_{H},x)} gate: the transform gate T ( W T , x ) {\displaystyle T(W_{T},x)} and the carry gate C ( W C , x ) {\displaystyle C(W_{C},x)} . The latter two gates are non-linear transfer functions (specifically sigmoid by convention). The function H {\displaystyle H} can be any desired transfer function. The carry gate is defined as: C ( W C , x ) = 1 − T ( W T , x ) {\displaystyle C(W_{C},x)=1-T(W_{T},x)} while the transform gate is just a gate with a sigmoid transfer function. == Structure == The structure of a hidden layer in the Highway Network follows the equation: y = H ( x , W H ) ⋅ T ( x , W T ) + x ⋅ C ( x , W C ) = H ( x , W H ) ⋅ T ( x , W T ) + x ⋅ ( 1 − T ( x , W T ) ) {\displaystyle {\begin{aligned}y=H(x,W_{H})\cdot T(x,W_{T})+x\cdot C(x,W_{C})\\=H(x,W_{H})\cdot T(x,W_{T})+x\cdot (1-T(x,W_{T}))\end{aligned}}} == Related work == Sepp Hochreiter analyzed the vanishing gradient problem in 1991 and attributed to it the reason why deep learning did not work well. To overcome this problem, Long Short-Term Memory (LSTM) recurrent neural networks have residual connections with a weight of 1.0 in every LSTM cell (called the constant error carrousel) to compute y t + 1 = F ( x t ) + x t {\textstyle y_{t+1}=F(x_{t})+x_{t}} . During backpropagation through time, this becomes the residual formula y = F ( x ) + x {\textstyle y=F(x)+x} for feedforward neural networks. This enables training very deep recurrent neural networks with a very long time span t. A later LSTM version published in 2000 modulates the identity LSTM connections by so-called "forget gates" such that their weights are not fixed to 1.0 but can be learned. In experiments, the forget gates were initialized with positive bias weights, thus being opened, addressing the vanishing gradient problem. As long as the forget gates of the 2000 LSTM are open, it behaves like the 1997 LSTM. The Highway Network of May 2015 applies these principles to feedforward neural networks. It was reported to be "the first very deep feedforward network with hundreds of layers". It is like a 2000 LSTM with forget gates unfolded in time, while the later Residual Nets have no equivalent of forget gates and are like the unfolded original 1997 LSTM. If the skip connections in Highway Networks are "without gates," or if their gates are kept open (activation 1.0), they become Residual Networks. The residual connection is a special case of the "short-cut connection" or "skip connection" by Rosenblatt (1961) and Lang & Witbrock (1988) which has the form x ↦ F ( x ) + A x {\displaystyle x\mapsto F(x)+Ax} . Here the randomly initialized weight matrix A does not have to be the identity mapping. Every residual connection is a skip connection, but almost all skip connections are not residual connections. The original Highway Network paper not only introduced the basic principle for very deep feedforward networks, but also included experimental results with 20, 50, and 100 layers networks, and mentioned ongoing experiments with up to 900 layers. Networks with 50 or 100 layers had lower training error than their plain network counterparts, but no lower training error than their 20 layers counterpart (on the MNIST dataset, Figure 1 in ). No improvement on test accuracy was reported with networks deeper than 19 layers (on the CIFAR-10 dataset; Table 1 in ). The ResNet paper, however, provided strong experimental evidence of the benefits of going deeper than 20 layers. It argued that the identity mapping without modulation is crucial and mentioned that modulation in the skip connection can still lead to vanishing signals in forward and backward propagation (Section 3 in ). This is also why the forget gates of the 2000 LSTM were initially opened through positive bias weights: as long as the gates are open, it behaves like the 1997 LSTM. Similarly, a Highway Net whose gates are opened through strongly positive bias weights behaves like a ResNet. The skip connections used in modern neural networks (e.g., Transformers) are dominantly identity mappings.
MicroTCA
MicroTCA (short for Micro Telecommunications Computing Architecture, also: μTCA) is a modular, open standard, created and maintained by the PCI Industrial Computer Manufacturers Group (PICMG). It provides the electrical, mechanical, thermal and management specifications to create a switched fabric computer system, using Advanced Mezzanine Cards (AMC), connected directly to a backplane. MicroTCA is a descendant of the AdvancedTCA standard. == History == The rapid expansion of mobile telecommunications and their associated services (such as text messages) at the beginning of the millennium increased the demand of processing power in telecommunication systems. The existing "carrier grade" (see RAS) computing architectures were not fit to house the high performance processors of the time. In order to answer those demands, about 100 companies worked together in PICMG, resulting in the Advanced Telecommunications Architecture (AdvancedTCA, ATCA), published in 2002. After the introduction of AdvancedTCA, a standard was developed, to cater towards smaller telecommunications systems at the edge of the network. This standard was geared towards a more compact, less expensive systems, without cutting back on reliability or data throughput. This standard, called MicroTCA, was ratified 2006. MicroTCA systems migrated after its release into non-telecommunication sectors, like defence, avionics and science. This resulted in extensions to the base-standard, called modules. == Modules == === MicroTCA.0 === The base-specification for properties common to all other modules, ratified July 6, 2006. This includes: Mechanical specifications, like possible dimensions of card cages, backplanes and supported AMC-modules Electrical specifications, like power distribution and interface layout Thermal specifications, like possible cooling layouts or available cooling power Management specifications A second revision of the base-specifications was ratified January 16, 2020, containing some corrections, as well as alterations, necessary to implement higher speed Ethernet fabrics, like 10GBASE-KR and 40GBASE-KR4. === MicroTCA.1 === This module adds specifications for ruggedized systems, using forced air for cooling. Possible scenarios for MicroTCA.1-based systems include outside plant telecom, industrial and aerospace environments === MicroTCA.2 === This module adds specifications for more stringent requirements with regards to temperature, shock, vibration and other environmental conditions. These specifications are geared towards use in outside plant telecom, machine and transport industry, as well as military airborne, shipboard and ground mobile equipment. MicroTCA.2 allows the use of air- and conduction-cooled AMC-modules. === MicroTCA.3 === This module adds specifications for even more stringent requirements with regards to temperature, shock, vibration and other environmental conditions. These specifications are geared towards use in outside plant telecom, machine and transport industry, as well as military airborne, shipboard and ground mobile equipment. MicroTCA.3 requires the use of conduction-cooled AMC-modules. === MicroTCA.4 === This module extends the AMC with a Rear Transition Module (RTM), increasing PCB-space and modularity. AMC and RTM are connected with a connector, located in zone 3, defined in MicroTCA.0. These specifications are geared towards use in large-scale scientific devices, like particle accelerators or telescopes. == Components of MicroTCA == === Card Cage === The card cage (also: shelf, crate) houses all the other components and as such has two primary functions: Provide mechanical stability to the other components Ensure sufficient cooling There exist a wide array of card cages. They usually differ in: the type of modules they support (MTCA.0, MTCA.1, ...) the number of slots they provide (typically between 2 and 12) the architecture of the installed backplane (see below) the cooling scheme they use (i.e. airflow front-to-back, bottom-to-top, side-to-side, conductive,...) === Backplane === The backplane is a printed circuit board, mounted directly into the card cage. It connects all other components of a MicroTCA system to each other and provides power, data access and management access to them. Two types of power are distributed over the backplane, Management Power (+3.3 V) and Payload Power (+12 V). Unlike typical backplanes, where power is distributed to all components via a common "powerplane" in the PCB, on a MicroTCA backplane, Management and Payload Power are distributed to each component individually. While Management Power is provided to each module connected to a powered backplane, Payload Power has to be granted by the MicroTCA Carrier Hub (MCH), after ensuring that the module is MicroTCA-compatible. The standard defines various communication buses, which the backplane can/should provide: Gigabit Ethernet IPMI SATA Fat pipe (can be used for PCIe, SRIO or 10G/40G Ethernet) Point to Point Links Clocks JTAG === Cooling Unit === The Cooling Unit (CU) provides controlled air flow in air-flow-cooled card cages. It usually consists of an array of fans and a controller, which is connected to the backplane. The MicroTCA Carrier Hub (MCH) can read-out temperature sensors (if present) and fan speed, as well as change fan speed via IPMI. The Cooling Unit is usually fitted to a specific card cage. Some CUs are easily detachable (i.e. for cleaning or replacement), while other card cages come with integrated, non-detachable CUs. === Power Module === The Power Module (PM, also: Power Supply) converts the AC power from the power line to the +3.3 V Management Power (MP) and +12 V Payload Power (PP), both of which are DC. There exist a variety of power modules, which differ in: form factor (i.e. double width, single width) input voltage (110 V, 220 V, both) output power (i.e. 600 W, 1000 W) The power module senses the presence of a module in a slot via a specified pin in the module connector, and immediately provides that module with management power. Payload power is managed by the MicroTCA Carrier Hub (MCH), which communicates with the power module via IPMI. The power module uses its own type of connector, and can thus only be installed into designated slots, which in turn can't carry any other type of module. Some card cages provide an additional power module slot for redundancy. In such a case, one slot is the primary, which will provide power by default, and the other one is secondary, providing power only, if the primary does not. === MicroTCA Carrier Hub === The MicroTCA Carrier Hub (MCH) is the central managing device of a MicroTCA card cage. It manages power distribution and cooling. It usually also provides Gigabit Ethernet and/or PCIe/Serial RapidIO switching. Some MCHs additionally provide clocking. As the name indicates, they are the hub of various star topologies (i.e. for Ethernet, PCIe) on the backplane and thus require dedicated slot(s). Some backplanes support two MCHs for redundancy. In this case there are two MCH slots, with one being designated primary, and one secondary. === Advanced Mezzanine Card === Advanced Mezzanine Card (AMC) is a standard for hot-pluggable PCBs. It was originally developed to be used in AdvancedTCA systems. The standard specifies: the dimensions of the PCB with two width variants (single, double) and three height variants (Compact, Mid-size, Full) type, location and orientation of connectors (i.e. Zone 1, 2, 3) There is a huge variation of functionalities, an AMC can fulfill: Computing (i.e. a module with CPU, RAM, SSD and on-board graphics) Storage (i.e. SSD carrier) Graphics card FPGA card (i.e. for signal processing) FMC carrier Digitizer card (Analog-Digital and Digital-Analog Conversion) Clocking and Triggering and others === Rear Transition Module (MTCA.4 only) === The Rear Transition Module (RTM) was added in the MicroTCA.4 standard. It is connected directly to an AMC via a connector, located in zone 3, requiring a double width AMC and RTM. An RTM has about the same dimensions, as an AMC, basically doubling the available PCB-space per slot in an MTCA.4 card cage. Its power is provided by the AMC. Thus an RTM can not operate on its own, but requires a paired AMC. The zone 3 connector is electrically free configurable, making it possible, that a mechanically fitting AMC-RTM pair is electrically incompatible. To avoid damage due to that incompatibility, a mechanical code-pin was added to MTCA.4-compatible AMCs and RTMs, mechanically preventing the installation of an electrically incompatible RTM to an AMC. The functionality of RTMs includes, but is not limited to: RF-signal pre-/post-processing (i.e. filtering, Up-/Down-conversion, Vector De-/Modulation) Digital signal pre-/post-processing Clock-generation/-distribution Device interfaces Date storage CPU (only MCH-RTM)
Comparison of JavaScript-based web frameworks
This is a comparison of web frameworks for front-end web development that are reliant on JavaScript code for their behavior. == General information == == High-level framework comparison == JavaScript-based web application frameworks, such as React and Vue, provide extensive capabilities but come with associated trade-offs. These frameworks often extend or enhance features available through native web technologies, such as routing, component-based development, and state management. While native web standards, including Web Components, modern JavaScript APIs like Fetch and ES Modules, and browser capabilities like Shadow DOM, have advanced significantly, frameworks remain widely used for their ability to enhance developer productivity, offer structured patterns for large-scale applications, simplify handling edge cases, and provide tools for performance optimization. Frameworks can introduce abstraction layers that may contribute to performance overhead, larger bundle sizes, and increased complexity. Modern frameworks, such as React 18 and Vue 3, address these challenges with features like concurrent rendering, tree-shaking, and selective hydration. While these advancements improve rendering efficiency and resource management, their benefits depend on the specific application and implementation context. Lightweight frameworks, such as Svelte and Preact, take different architectural approaches, with Svelte eliminating the virtual DOM entirely in favor of compiling components to efficient JavaScript code, and Preact offering a minimal, compatible alternative to React. Framework choice depends on an application’s requirements, including the team’s expertise, performance goals, and development priorities. A newer category of web frameworks, including enhance.dev, Astro, and Fresh, leverages native web standards while minimizing abstractions and development tooling. These solutions emphasize progressive enhancement, server-side rendering, and optimizing performance. Astro renders static HTML by default while hydrating only interactive parts. Fresh focuses on server-side rendering with zero runtime overhead. Enhance.dev prioritizes progressive enhancement patterns using Web Components. While these tools reduce reliance on client-side JavaScript by shifting logic to build-time or server-side execution, they still use JavaScript where necessary for interactivity. This approach makes them particularly suitable for performance-critical and content-focused applications. == Features == == Browser support ==
Web testing
Web testing is software testing that focuses on web applications. Complete testing of a web-based system before going live can help address issues before the system is revealed to the public. Issues may include the security of the web application, the basic functionality of the site, its accessibility to disabled and fully able users, its ability to adapt to the multitude of desktops, devices, and operating systems, as well as readiness for expected traffic and number of users and the ability to survive a massive spike in user traffic, both of which are related to load testing. == Web application performance tool == A web application performance tool (WAPT) is used to test web applications and web related interfaces. These tools are used for performance, load and stress testing of web applications, web sites, web API, web servers and other web interfaces. WAPT tends to simulate virtual users which will repeat either recorded URLs or specified URL and allows the users to specify number of times or iterations that the virtual users will have to repeat the recorded URLs. By doing so, the tool is useful to check for bottleneck and performance leakage in the website or web application being tested. A WAPT faces various challenges during testing and should be able to conduct tests for: Browser compatibility Operating System compatibility Windows application compatibility where required WAPT allows a user to specify how virtual users are involved in the testing environment.ie either increasing users or constant users or periodic users load. Increasing user load, step by step is called RAMP where virtual users are increased from 0 to hundreds. Constant user load maintains specified user load at all time. Periodic user load tends to increase and decrease the user load from time to time. == Web security testing == Web security testing tells us whether Web-based applications requirements are met when they are subjected to malicious input data. There is a web application security testing plug-in collection for Fire Fox == Web API testing == An application programming interface API exposes services to other software components, which can query the API. The API implementation is in charge of computing the service and returning the result to the component that send the query. A part of web testing focuses on testing these web API implementations. GraphQL is a specific query and API language. It is the focus of tailored testing techniques. Search-based test generation yields good results to generate test cases for GraphQL APIs.
Ogle app
Ogle is a free smartphone based social media application. It is available for iOS and Android. Ogle acts like a school wide forum that lets users and users' classmates share and interact. Users can share photos, videos, questions, even thoughts and watch submissions grow in popularity as other users vote and comment on them. == App Features == Campus Feed: Interact by watching and posting videos or pictures to your campus story. Photos and Videos: share what you want with many different timing options. Interact: Chat with friends and groups, or share a moment for all to see. Real-name system: choose to register an account with username and profile picture. Custom Stickers: Create stickers to add creativity and zest to your pictures. Flash Interaction: All private chat and group chat history will be deleted after 24 hours on Ogle Chat. == Controversies == Users can post anything on Ogle using text, photos, and videos. As a result, some Ogle user's sense of anonymity, posts have targeted specific schools and students with abusive and hurtful content. The Ogle app's user anonymity makes it difficult for school officials to quickly investigate issues that occur within the Ogle app. On March 28, 2016, three people were arrested after violent threats were made against an Anaheim high school. 18-year-old Miguel Meza was arrested Sunday afternoon during a traffic stop, along with his passenger, 23-year-old Johnny Aguilar. Police said both men had loaded handguns. Aguilar was also accused of violating his probation. "It is concerning the fact that they did have firearms, but we don't have a crystal ball. We can't determine if they possessed those firearms to engage in some kind of school violence or if they had it for another reason," Sgt. Daron Wyatt with the Anaheim Police Department said. Officials said Meza and Aguilar have known gang ties and detectives began investigating Meza after threats were made against the school on Ogle. On February 29, 2016, Santa Cruz County sheriff's deputies arrested a 16-year-old Aptos High School student Friday, accused of making an online threat of gun violence at Aptos High and Monte Vista Christian."He basically told detectives that it was all a joke. It's not a joke. You have multiple resources being spent to investigate these cases," said Santa Cruz County Sheriff's Sgt. Roy Morales. The schools remained open throughout the week, with a huge police presence on campus. In an anonymous emailed statement to the Daily Pilot on Thursday, the "Ogle team" said: "We are aware of the concern, and cyberbullying is absolutely NOT our intention for the app. Our goal for this app is to create a free and safe community space for students, for a better communication. We are currently working around the clock to improve the app. As a matter of fact, we are also in contact with local police departments, anti-bullying organizations and local high schools to try to help the students." In response to these incidents, Ogle expressed that they takes the safety of its users seriously and does not condone any type of behavior that is illegal or in violation of its content policies. The company also said it has instituted a content moderation team to increase review and identify and remove inappropriate content, and take action against “those who violate our community guidelines.”
Zero-overhead looping
In computer architecture, zero-overhead looping is a hardware feature found in some processors that enables loops to execute without the performance cost of traditional loop control instructions. Instead of software managing loop iterations, the processor's hardware handles repetition automatically, saving clock cycles and improving efficiency. This technique is commonly employed in digital signal processors (DSPs) and certain complex instruction set computer (CISC) architectures. == Background == In many instruction sets, a loop must be implemented by using instructions to increment or decrement a counter, check whether the end of the loop has been reached, and if not jump to the beginning of the loop so it can be repeated. Although this typically only represents around 3–16 bytes of space for each loop, even that small amount could be significant depending on the size of the CPU caches. More significant is that those instructions each take time to execute, time which is not spent doing useful work. The overhead of such a loop is apparent compared to a completely unrolled loop, in which the body of the loop is duplicated exactly as many times as it will execute. In that case, no space or execution time is wasted on instructions to repeat the body of the loop. However, the duplication caused by loop unrolling can significantly increase code size, and the larger size can even impact execution time due to cache misses. (For this reason, it's common to only partially unroll loops, such as transforming it into a loop which performs the work of four iterations in one step before repeating. This balances the advantages of unrolling with the overhead of repeating the loop.) Moreover, completely unrolling a loop is only possible for a limited number of loops: those whose number of iterations is known at compile time. For example, the following C code could be compiled and optimized into the following x86 assembly code: == Implementation == Processors with zero-overhead looping have machine instructions and registers to automatically repeat one or more instructions. Depending on the instructions available, these may only be suitable for count-controlled loops ("for loops") in which the number of iterations can be calculated in advance, or only for condition-controlled loops ("while loops") such as operations on null-terminated strings. === Examples === ==== PIC ==== In the PIC instruction set, the REPEAT and DO instructions implement zero-overhead loops. REPEAT only repeats a single instruction, while DO repeats a specified number of following instructions. ==== Blackfin ==== Blackfin offers two zero-overhead loops. The loops can be nested; if both hardware loops are configured with the same "loop end" address, loop 1 will behave as the inner loop and repeat, and loop 0 will behave as the outer loop and repeat only if loop 1 would not repeat. Loops are controlled using the LTx and LBx registers (x either 0 to 1) to set the top and bottom of the loop — that is, the first and last instructions to be executed, which can be the same for a loop with only one instruction — and LCx for the loop count. The loop repeats if LCx is nonzero at the end of the loop, in which case LCx is decremented. The loop registers can be set manually, but this would typically consume 6 bytes to load the registers, and 8–16 bytes to set up the values to be loaded. More common is to use the loop setup instruction (represented in assembly as either LOOP with pseudo-instruction LOOP_BEGIN and LOOP_END, or in a single line as LSETUP), which optionally initializes LCx and sets LTx and LBx to the desired values. This only requires 4–6 bytes, but can only set LTx and LBx within a limited range relative to where the loop setup instruction is located. ==== x86 ==== The x86 assembly language REP prefixes implement zero-overhead loops for a few instructions (namely MOVS/STOS/CMPS/LODS/SCAS). Depending on the prefix and the instruction, the instruction will be repeated a number of times with (E)CX holding the repeat count, or until a match (or non-match) is found with AL/AX/EAX or with DS:[(E)SI]. This can be used to implement some types of searches and operations on null-terminated strings.