Snake oil (cryptography)

Snake oil (cryptography)

In cryptography, snake oil is any cryptographic method or product considered to be bogus or fraudulent. The name derives from snake oil, one type of patent medicine widely available in the 19th century United States. Distinguishing secure cryptography from insecure cryptography can be difficult from the viewpoint of a user. Many cryptographers, such as Bruce Schneier and Phil Zimmermann, undertake to educate the public in how secure cryptography is done, as well as highlighting the misleading marketing of some cryptographic products. The Snake Oil FAQ describes itself as "a compilation of common habits of snake oil vendors. It cannot be the sole method of rating a security product, since there can be exceptions to most of these rules. [...] But if you're looking at something that exhibits several warning signs, you're probably dealing with snake oil." == Some examples of snake oil cryptography techniques == This is not an exhaustive list of snake oil signs. A more thorough list is given in the references. Secret system Some encryption systems will claim to rely on a secret algorithm, technique, or device; this is categorized as security through obscurity. Criticisms of this are twofold. First, a 19th-century rule known as Kerckhoffs's principle, later formulated as Shannon's maxim, teaches that "the enemy knows the system" and the secrecy of a cryptosystem algorithm does not provide any advantage. Second, secret methods are not open to public peer review and cryptanalysis, so potential mistakes and insecurities can go unnoticed. Technobabble Snake oil salespeople may use "technobabble" to sell their product since cryptography is a complicated subject. "Unbreakable" Claims of a system or cryptographic method being "unbreakable" are always false (or true under some limited set of conditions), and are generally considered a sure sign of snake oil. "Military grade" There is no accepted standard or criterion for "military grade" ciphers. One-time pads One-time pads are a popular cryptographic method to invoke in advertising, because it is well known that one-time pads, when implemented correctly, are genuinely unbreakable. The problem comes in implementing one-time pads, which is rarely done correctly. Cryptographic systems that claim to be based on one-time pads are considered suspect, particularly if they do not describe how the one-time pad is implemented, or they describe a flawed implementation. Unsubstantiated "bit" claims Cryptographic products are often accompanied with claims of using a high number of bits for encryption, apparently referring to the key length used. However key lengths are not directly comparable between symmetric and asymmetric systems. Furthermore, the details of implementation can render the system vulnerable. For example, in 2008 it was revealed that a number of hard drives sold with built-in "128-bit AES encryption" were actually using a simple and easily defeated "XOR" scheme. AES was only used to store the key, which was easy to recover without breaking AES.

Vision transformer

A vision transformer (ViT) is a transformer designed for computer vision. A ViT decomposes an input image into a series of patches (rather than text into tokens), serializes each patch into a vector, and maps it to a smaller dimension with a single matrix multiplication. These vector embeddings are then processed by a transformer encoder as if they were token embeddings. ViTs were designed as alternatives to convolutional neural networks (CNNs) in computer vision applications. They have different inductive biases, training stability, and data efficiency. Compared to CNNs, ViTs are less data efficient, but have higher capacity. Some of the largest modern computer vision models are ViTs, such as one with 22B parameters. Subsequent to its publication, many variants were proposed, with hybrid architectures with both features of ViTs and CNNs. ViTs have found application in image recognition, image segmentation, weather prediction, and autonomous driving. == History == Transformers were introduced in Attention Is All You Need (2017), and have found widespread use in natural language processing. A 2019 paper applied ideas from the Transformer to computer vision. Specifically, they started with a ResNet, a standard convolutional neural network used for computer vision, and replaced all convolutional kernels by the self-attention mechanism found in a Transformer. It resulted in superior performance. However, it is not a Vision Transformer. In 2020, an encoder-only Transformer was adapted for computer vision, yielding the ViT, which reached state of the art in image classification, overcoming the previous dominance of CNN. The masked autoencoder (2022) extended ViT to work with unsupervised training. The vision transformer and the masked autoencoder, in turn, stimulated new developments in convolutional neural networks. Subsequently, there was cross-fertilization between the previous CNN approach and the ViT approach. In 2021, some important variants of the Vision Transformers were proposed. These variants are mainly intended to be more efficient, more accurate or better suited to a specific domain. Two studies improved efficiency and robustness of ViT by adding a CNN as a preprocessor. The Swin Transformer achieved state-of-the-art results on some object detection datasets such as COCO, by using convolution-like sliding windows of attention mechanism, and the pyramid process in classical computer vision. == Overview == The basic architecture, used by the original 2020 paper, is as follows. In summary, it is a BERT-like encoder-only Transformer. The input image is of type R H × W × C {\displaystyle \mathbb {R} ^{H\times W\times C}} , where H , W , C {\displaystyle H,W,C} are height, width, channel (RGB). It is then split into square-shaped patches of type R P × P × C {\displaystyle \mathbb {R} ^{P\times P\times C}} . For each patch, the patch is pushed through a linear operator, to obtain a vector ("patch embedding"). The position of the patch is also transformed into a vector by "position encoding" (the paper tried no embedding, 1D embedding, 2D embedding, and relative embedding: 1D was adopted). The two vectors are added, then pushed through several Transformer encoders. The attention mechanism in a ViT repeatedly transforms representation vectors of image patches, incorporating more and more semantic relations between image patches in an image. This is analogous to how in natural language processing, as representation vectors flow through a transformer, they incorporate more and more semantic relations between words, from syntax to semantics. The above architecture turns an image into a sequence of vector representations. To use these for downstream applications, an additional head needs to be trained to interpret them. For example, to use it for classification, one can add a shallow MLP on top of it that outputs a probability distribution over classes. The original paper uses a linear-GeLU-linear-softmax network. == Variants == === Original ViT === The original ViT was an encoder-only Transformer supervise-trained to predict the image label from the patches of the image. As in the case of BERT, it uses a special token in the input side, and the corresponding output vector is used as the only input of the final output MLP head. The special token is an architectural hack to allow the model to compress all information relevant for predicting the image label into one vector. Transformers found their initial applications in natural language processing tasks, as demonstrated by language models such as BERT and GPT-3. By contrast the typical image processing system uses a convolutional neural network (CNN). Well-known projects include Xception, ResNet, EfficientNet, DenseNet, and Inception. Transformers measure the relationships between pairs of input tokens (words in the case of text strings), termed attention. The cost is quadratic in the number of tokens. For images, the basic unit of analysis is the pixel. However, computing relationships for every pixel pair in a typical image is prohibitive in terms of memory and computation. Instead, ViT computes relationships among pixels in various small sections of the image (e.g., 16x16 pixels), at a drastically reduced cost. The sections (with positional embeddings) are placed in a sequence. The embeddings are learnable vectors. Each section is arranged into a linear sequence and multiplied by the embedding matrix. The result, with the position embedding is fed to the transformer. === Architectural improvements === ==== Pooling ==== After the ViT processes an image, it produces some embedding vectors. These must be converted to a single class probability prediction by some kind of network. In the original ViT and Masked Autoencoder, they used a dummy [CLS] token, in emulation of the BERT language model. The output at [CLS] is the classification token, which is then processed by a LayerNorm-feedforward-softmax module into a probability distribution. Global average pooling (GAP) does not use the dummy token, but simply takes the average of all output tokens as the classification token. It was mentioned in the original ViT as being equally good. Multihead attention pooling (MAP) applies a multiheaded attention block to pooling. Specifically, it takes as input a list of vectors x 1 , x 2 , … , x n {\displaystyle x_{1},x_{2},\dots ,x_{n}} , which might be thought of as the output vectors of a layer of a ViT. The output from MAP is M u l t i h e a d e d A t t e n t i o n ( Q , V , V ) {\displaystyle \mathrm {MultiheadedAttention} (Q,V,V)} , where q {\displaystyle q} is a trainable query vector, and V {\displaystyle V} is the matrix with rows being x 1 , x 2 , … , x n {\displaystyle x_{1},x_{2},\dots ,x_{n}} . This was first proposed in the Set Transformer architecture. Later papers demonstrated that GAP and MAP both perform better than BERT-like pooling. A variant of MAP was proposed as class attention, which applies MAP, then feedforward, then MAP again. Re-attention was proposed to allow training deep ViT. It changes the multiheaded attention module. === Masked Autoencoder === The Masked Autoencoder took inspiration from denoising autoencoders and context encoders. It has two ViTs put end-to-end. The first one ("encoder") takes in image patches with positional encoding, and outputs vectors representing each patch. The second one (called "decoder", even though it is still an encoder-only Transformer) takes in vectors with positional encoding and outputs image patches again. ==== Training ==== During training, input images (224px x 224 px in the original implementation) are split along a designated number of lines on each axis, producing image patches. A certain percentage of patches are selected to be masked out by mask tokens, while all others are retained in the image. The network is tasked with reconstructing the image from the remaining unmasked patches. Mask tokens in the original implementation are learnable vector quantities. A linear projection with positional embeddings is then applied to the vector of unmasked patches. Experiments varying mask ratio on networks trained on the ImageNet-1K dataset found 75% mask ratios achieved high performance on both finetuning and linear-probing of the encoder's latent space. The MAE processes only unmasked patches during training, increasing the efficiency of data processing in the encoder and lowering the memory usage of the transformer. A less computationally-intensive ViT is used for the decoder in the original implementation of the MAE. Masked patches are added back to the output of the encoder block as mask tokens and both are fed into the decoder. A reconstruction loss is computed for the masked patches to assess network performance. ==== Prediction ==== In prediction, the decoder architecture is discarded entirely. The input image is split into patches by the same algorithm as in training, but no patches are masked out. A linear projection wi

VibeOS

VibeOS is an operating system built from scratch entirely by generative artificial intelligence, using code produced through prompts to Claude (vibe coding). It is capable of running on QEMU and was successfully tested on a Raspberry Pi Zero. It has been released under the MIT license. == Features == === Core === Custom kernel with cooperative multitasking (preemptive backup) FAT32 filesystem with long filename support Memory allocator, process scheduler, interrupt handling GIC-400 (QEMU) and BCM2836/BCM2835 (Pi) interrupt controllers Configurable boot (splash screen, boot target) === GUI === Desktop environment with draggable windows Menu bar, dock, window minimize/maximize/close Mouse and keyboard input Modern macOS-inspired aesthetic === Networking === Full TCP/IP stack (Ethernet, ARP, IP, ICMP, UDP, TCP) DNS resolver HTTP client TLS 1.2 with HTTPS support === Apps === Web browser with HTML/CSS rendering Terminal emulator with readline-style shell Text editor (vim clone) with syntax highlighting File manager with drag-and-drop Music player (MP3/WAV) Calculator, system monitor VibeCode IDE Doom port === Development === TCC (Tiny C Compiler) - compile C programs directly on VibeOS MicroPython interpreter with full kernel API bindings 60+ userspace programs (coreutils, games, GUI apps) === Hardware === Runs on Raspberry Pi Zero 2W USB keyboard and mouse via DWC2 driver SD card via EMMC driver 1920×1080 framebuffer == Further projects == There are other independent projects under the VibeOS name, including an independent development by Ben, also developed using vibe coding, aimed at creating a Unix-like operating system for educational purposes. Another project is Vib-OS, an operating system also built using vibe coding, capable of booting on a Raspberry Pi. It offers a desktop environment with a customizable wallpaper, a file manager, and a web browser currently in an early stage of development, a functional Doom port, among other features that are not very polished given the state of development.

GeForce RTX 50 series

The GeForce RTX 50 series of consumer graphics cards is the successor of Nvidia's GeForce 40 series. Announced at CES 2025, it debuted with the release of the RTX 5070, RTX 5080 and RTX 5090 in January 2025. It is based on Nvidia's Blackwell architecture featuring Nvidia RTX's fourth-generation RT cores for hardware-accelerated real-time ray tracing, and fifth-generation deep learning–focused Tensor Cores. The GPUs are manufactured by TSMC on a custom 4N process node. == Background == In March 2024, Nvidia announced the Blackwell architecture for its datacenter products. Like Ampere, the architecture is shared by consumer and datacenter products rather than having distinct architectures released simultaneously like Ada Lovelace for consumers and Hopper for datacenter. At the Game Awards in December 2024, a cinematic trailer for The Witcher IV was shown that had been pre-rendered on an "unannounced Nvidia GeForce RTX GPU". This was assumed to be an upcoming GeForce RTX 50 series GPU. Following the RTX 50 series announcement, Nvidia confirmed that the trailer was "pre-rendered in Unreal Engine 5 on a GeForce RTX 5090". Later in the same month, it was reported that Nvidia had begun stockpiling GeForce RTX 50 series units in U.S. warehouses due to a threatened 10% import tariff and 60% tariff on Chinese imports that Donald Trump promised in his re-election campaign. === Announcement === On January 6, 2025, the GeForce RTX 50 series was officially announced for desktop and mobile devices during Nvidia's CES keynote in Las Vegas. The pricing announcement was met with surprise as the RTX 5080 at $999 was the same price that the RTX 4080 Super released at a year earlier despite the anticipated price increases. Nvidia CEO Jensen Huang falsely claimed that the RTX 5070 could reach "RTX 4090 performance at $549", a figure that relies on the use of DLSS 4 upscaling and Multi Frame generation, and is not an indication of raw performance. == Features == === Blackwell architecture === The GeForce RTX 50 series is powered by the Blackwell microarchitecture, which continues Ada Lovelace's emphasis on high graphics frequencies and large L2 caches. The Blackwell architecture introduces Nvidia RTX's fourth-generation RT cores for hardware-accelerated real-time ray tracing and fifth-generation Tensor Cores for AI compute and performing floating-point calculations. === GDDR7 === RTX 50 series GPUs are the first consumer GPUs to feature GDDR7 video memory for greater memory bandwidth over the same bus width compared to the GDDR6 and GDDR6X memory used in the GeForce 40 series. RTX 50 series desktop GPUs use GDDR7 modules from Samsung due to them being available for validation earlier than modules from SK Hynix and Micron. === 12V-2×6 connector === The GeForce RTX 50 series uses the 16-pin 12V-2×6 connector, which is a revision of the 12VHPWR connector featured on the GeForce 40 series. There were problems with the 12VHPWR connector melting on some RTX 4090 GPUs due to the connector not being fully seated and connector design flaws that did not implement a high enough safety and error tolerance. The 12V-2×6 connector revision, published by PCI-SIG in July 2023, addressed this by shortening the four sense pins so the connector will not push any power if it has not been fully seated. The 12VHPWR design would still draw up to 150W of power even if the sense pins were not making full contact. 12V-2×6 is backwards compatible with existing 12VHPWR cables and adapters. Nvidia has mandated to its AIB partners that the 16-pin 12V-2×6 connector be used on all RTX 50 series designs. With the GeForce 40 series, the 12VHPWR connector was only mandated on higher power cards such as the RTX 4070 Super, RTX 4070 Ti, RTX 4070 Ti Super, RTX 4080, RTX 4080 Super and RTX 4090 while RTX 4060, RTX 4060 Ti and RTX 4070 AIB designs had the option of using 8-pin PCIe connectors. The 600W-capable 12VHPWR connector would not have been necessary on sub-200W cards. === DLSS 4 === The fourth generation of Deep Learning Super Sampling (DLSS) was unveiled alongside the RTX 50 series. DLSS 4 upscaling uses a new vision transformer-based model for enhanced image quality with reduced ghosting and greater image stability in motion compared to the previous convolutional neural network (CNN) model. DLSS 4 also allows a greater number of frames to be generated and interpolated based on a single traditionally rendered frame. This form of frame generation called Multi Frame Generation is exclusive to the RTX 50 series while the GeForce 40 series is limited to one interpolated frame per traditionally rendered frame. Nvidia claims that DLSS 4's frame generation model uses 30% less video memory with the example of Warhammer 40,000: Darktide using 400 MB less memory at 4K resolution with frame generation enabled. Nvidia claims that 75 titles will integrate DLSS 4 Multi Frame Generation at launch, including Alan Wake 2, Cyberpunk 2077, Indiana Jones and the Great Circle, and Star Wars Outlaws. === Media Engine and I/O === The RTX 50 series includes DisplayPort 2.1b UHBR20 (80Gbps) with higher display output data rates to support high resolution and high refresh rate displays. The GeForce 40 series received criticism for only including DisplayPort 1.4a (32Gbps) while the competing Radeon RX 7000 series included DisplayPort 2.1 UHBR13.5 (54Gbps). At CES 2025, VESA announced a collaboration with Nvidia on the new DP80LL ("low loss") UHBR20 active cable standard. DP80LL allows for 80Gbps DisplayPort 2.1 cables up to 3 meters long as passive DP80 cables are limited in length due to signal integrity concerns. The RTX 50 series introduces the ninth-generation NVENC encoder and sixth-generation NVDEC video decoder. For the first time in a consumer GeForce GPU, encoding and decoding video in the 4:2:2 color format for professional-grade higher color depth is supported. == List of GPUs == === Desktop === GeForce RTX 50 series desktop GPUs are the second consumer GPUs to utilize a PCIe 5.0 interface and the first to feature GDDR7 video memory (except for the entry level RTX 5050 that still uses GDDR6). They are fabricated by TSMC using a custom 5 nm process dubbed 4N. === Mobile === Laptops featuring GeForce RTX 50 series laptop GPUs were shown at CES 2025. Laptops with RTX 50 series GPUs were paired with Intel's Arrow Lake-HX and AMD's Strix Point and Fire Range CPUs. Nvidia claims that Blackwell architecture's new Max-Q features can increase battery life by up to 40% over GeForce 40 series laptops. For example, Advanced Power Gating saves power by turning off areas of the GPU that are unused and the paired GDDR7 memory can run in an "ultra" low-voltage state. Initial RTX 50 series laptops will become available in March 2025 starting at $1,299. == Controversies == === 12V-2x6 power connector issue === The 12V-2x6 connector used by multiple 5090 cards faces criticism due to a design flaw that can potentially cause the connector to melt. The flaw primarily affect Nvidia's own RTX 5090 FE and RTX 5080 FE cards and are similar to the failures seen on the RTX 40 series but models by third party OEMs have been affected as well. === Availability and pricing === The releases of the RTX 5090, 5080 and 5070 Ti were marked by severe availability issues and pricing well above MSRP. Pricing became an issue again at the end of 2025 due to an ongoing memory supply shortage. Nvidia has been rumored to cut production of 16GB VRAM cards, affecting the availability of the RTX 5060 Ti 16GB and RTX 5070 Ti SKUs. === 32-bit support removal for CUDA, OpenCL, and GPU PhysX === Support for 32-bit OpenCL, and CUDA applications (and as a result 32-bit GPU-accelerated PhysX), was dropped for the GeForce RTX 50 series, which resulted in several applications encountering performance issues with GPU PhysX options or not being able to run at all, causing negative reactions from numerous gaming communities. On December 4, 2025, with the release of driver version 591.44, 32-bit GPU-accelerated PhysX support was restored for certain games. Support for more games was promised in the future. === Incomplete dies and missing ROPs === The dies of certain RTX 5090/5090D, 5080, and 5070 Ti cards were missing eight render output units (ROPs), resulting in slower graphics while pure compute and AI workloads are unaffected. Nvidia claimed that less than 0.5% of cards are affected and that the "production anomaly" has been rectified. === Black screen issues === Some RTX 5080 and 5090 users reported an issue where the system would boot into a black screen after installing Nvidia drivers. Nvidia confirmed the issue and said that a new driver update would fix it for people who hadn't received a VBIOS update yet. Released on February 27, 2025 Nvidia drivers version 572.60 claim to have fixed the issue. Nvidia has since released multiple hotfix and Game Ready drivers that contain additional fixes for the issue. === Windows driver branch quality and stabilit

MicroTCA

MicroTCA (short for Micro Telecommunications Computing Architecture, also: μTCA) is a modular, open standard, created and maintained by the PCI Industrial Computer Manufacturers Group (PICMG). It provides the electrical, mechanical, thermal and management specifications to create a switched fabric computer system, using Advanced Mezzanine Cards (AMC), connected directly to a backplane. MicroTCA is a descendant of the AdvancedTCA standard. == History == The rapid expansion of mobile telecommunications and their associated services (such as text messages) at the beginning of the millennium increased the demand of processing power in telecommunication systems. The existing "carrier grade" (see RAS) computing architectures were not fit to house the high performance processors of the time. In order to answer those demands, about 100 companies worked together in PICMG, resulting in the Advanced Telecommunications Architecture (AdvancedTCA, ATCA), published in 2002. After the introduction of AdvancedTCA, a standard was developed, to cater towards smaller telecommunications systems at the edge of the network. This standard was geared towards a more compact, less expensive systems, without cutting back on reliability or data throughput. This standard, called MicroTCA, was ratified 2006. MicroTCA systems migrated after its release into non-telecommunication sectors, like defence, avionics and science. This resulted in extensions to the base-standard, called modules. == Modules == === MicroTCA.0 === The base-specification for properties common to all other modules, ratified July 6, 2006. This includes: Mechanical specifications, like possible dimensions of card cages, backplanes and supported AMC-modules Electrical specifications, like power distribution and interface layout Thermal specifications, like possible cooling layouts or available cooling power Management specifications A second revision of the base-specifications was ratified January 16, 2020, containing some corrections, as well as alterations, necessary to implement higher speed Ethernet fabrics, like 10GBASE-KR and 40GBASE-KR4. === MicroTCA.1 === This module adds specifications for ruggedized systems, using forced air for cooling. Possible scenarios for MicroTCA.1-based systems include outside plant telecom, industrial and aerospace environments === MicroTCA.2 === This module adds specifications for more stringent requirements with regards to temperature, shock, vibration and other environmental conditions. These specifications are geared towards use in outside plant telecom, machine and transport industry, as well as military airborne, shipboard and ground mobile equipment. MicroTCA.2 allows the use of air- and conduction-cooled AMC-modules. === MicroTCA.3 === This module adds specifications for even more stringent requirements with regards to temperature, shock, vibration and other environmental conditions. These specifications are geared towards use in outside plant telecom, machine and transport industry, as well as military airborne, shipboard and ground mobile equipment. MicroTCA.3 requires the use of conduction-cooled AMC-modules. === MicroTCA.4 === This module extends the AMC with a Rear Transition Module (RTM), increasing PCB-space and modularity. AMC and RTM are connected with a connector, located in zone 3, defined in MicroTCA.0. These specifications are geared towards use in large-scale scientific devices, like particle accelerators or telescopes. == Components of MicroTCA == === Card Cage === The card cage (also: shelf, crate) houses all the other components and as such has two primary functions: Provide mechanical stability to the other components Ensure sufficient cooling There exist a wide array of card cages. They usually differ in: the type of modules they support (MTCA.0, MTCA.1, ...) the number of slots they provide (typically between 2 and 12) the architecture of the installed backplane (see below) the cooling scheme they use (i.e. airflow front-to-back, bottom-to-top, side-to-side, conductive,...) === Backplane === The backplane is a printed circuit board, mounted directly into the card cage. It connects all other components of a MicroTCA system to each other and provides power, data access and management access to them. Two types of power are distributed over the backplane, Management Power (+3.3 V) and Payload Power (+12 V). Unlike typical backplanes, where power is distributed to all components via a common "powerplane" in the PCB, on a MicroTCA backplane, Management and Payload Power are distributed to each component individually. While Management Power is provided to each module connected to a powered backplane, Payload Power has to be granted by the MicroTCA Carrier Hub (MCH), after ensuring that the module is MicroTCA-compatible. The standard defines various communication buses, which the backplane can/should provide: Gigabit Ethernet IPMI SATA Fat pipe (can be used for PCIe, SRIO or 10G/40G Ethernet) Point to Point Links Clocks JTAG === Cooling Unit === The Cooling Unit (CU) provides controlled air flow in air-flow-cooled card cages. It usually consists of an array of fans and a controller, which is connected to the backplane. The MicroTCA Carrier Hub (MCH) can read-out temperature sensors (if present) and fan speed, as well as change fan speed via IPMI. The Cooling Unit is usually fitted to a specific card cage. Some CUs are easily detachable (i.e. for cleaning or replacement), while other card cages come with integrated, non-detachable CUs. === Power Module === The Power Module (PM, also: Power Supply) converts the AC power from the power line to the +3.3 V Management Power (MP) and +12 V Payload Power (PP), both of which are DC. There exist a variety of power modules, which differ in: form factor (i.e. double width, single width) input voltage (110 V, 220 V, both) output power (i.e. 600 W, 1000 W) The power module senses the presence of a module in a slot via a specified pin in the module connector, and immediately provides that module with management power. Payload power is managed by the MicroTCA Carrier Hub (MCH), which communicates with the power module via IPMI. The power module uses its own type of connector, and can thus only be installed into designated slots, which in turn can't carry any other type of module. Some card cages provide an additional power module slot for redundancy. In such a case, one slot is the primary, which will provide power by default, and the other one is secondary, providing power only, if the primary does not. === MicroTCA Carrier Hub === The MicroTCA Carrier Hub (MCH) is the central managing device of a MicroTCA card cage. It manages power distribution and cooling. It usually also provides Gigabit Ethernet and/or PCIe/Serial RapidIO switching. Some MCHs additionally provide clocking. As the name indicates, they are the hub of various star topologies (i.e. for Ethernet, PCIe) on the backplane and thus require dedicated slot(s). Some backplanes support two MCHs for redundancy. In this case there are two MCH slots, with one being designated primary, and one secondary. === Advanced Mezzanine Card === Advanced Mezzanine Card (AMC) is a standard for hot-pluggable PCBs. It was originally developed to be used in AdvancedTCA systems. The standard specifies: the dimensions of the PCB with two width variants (single, double) and three height variants (Compact, Mid-size, Full) type, location and orientation of connectors (i.e. Zone 1, 2, 3) There is a huge variation of functionalities, an AMC can fulfill: Computing (i.e. a module with CPU, RAM, SSD and on-board graphics) Storage (i.e. SSD carrier) Graphics card FPGA card (i.e. for signal processing) FMC carrier Digitizer card (Analog-Digital and Digital-Analog Conversion) Clocking and Triggering and others === Rear Transition Module (MTCA.4 only) === The Rear Transition Module (RTM) was added in the MicroTCA.4 standard. It is connected directly to an AMC via a connector, located in zone 3, requiring a double width AMC and RTM. An RTM has about the same dimensions, as an AMC, basically doubling the available PCB-space per slot in an MTCA.4 card cage. Its power is provided by the AMC. Thus an RTM can not operate on its own, but requires a paired AMC. The zone 3 connector is electrically free configurable, making it possible, that a mechanically fitting AMC-RTM pair is electrically incompatible. To avoid damage due to that incompatibility, a mechanical code-pin was added to MTCA.4-compatible AMCs and RTMs, mechanically preventing the installation of an electrically incompatible RTM to an AMC. The functionality of RTMs includes, but is not limited to: RF-signal pre-/post-processing (i.e. filtering, Up-/Down-conversion, Vector De-/Modulation) Digital signal pre-/post-processing Clock-generation/-distribution Device interfaces Date storage CPU (only MCH-RTM)

Army Chief Information Officer/G-6

In September 2020, the Army realigned the previously consolidated CIO/G-6 function into two separate roles, Office of the Chief Information Officer and Deputy Chief of Staff, G-6, that report to the secretary of the Army and chief of staff of the Army, respectively. The realignment came after several months of planning and coordination. Lt. Gen. John Morrison was nominated to the Senate for promotion and assignment as the G-6 and confirmed, assuming that position in August 2020. Subsequently, the Secretary of the Army, Ryan McCarthy appointed Dr. Raj G. Iyer as the first civilian Chief Information Officer, a career Senior Executive Service position in November 2020. == G-6 == Advise chief of staff of the Army and the Chief Information Officer on planning, fielding, and execution of C4IT worldwide Army operations Develop and execute the plan for the Unified Network Implement Army information assurance Supervise C4IT, Signal support, Information security, Force structure and equipping activities in support of warfighting operations Oversee management of the Signal forces == Planned realignment == On June 11, 2020, the Army announced that the two roles of CIO and Deputy Chief of Staff, G-6 (DCS, G-6) would be realigned no later than August 31, 2020, with separate individuals responsible for each position. With the realignment: CIO core functions will be policy, governance, and oversight. Focus areas include: Information Environment, Cybersecurity, Enterprise Architecture, and Data Policy/Oversight/Governance, Enterprise Architecture, Enterprise Cloud Management and IT Spend/Category Management. DCS, G-6 core functions will be planning, strategy, and implementation. Focus areas include: Information Environment/Network, Planning and Integration, Theater Synchronization, Architecture Integration, Enterprise Information Environment (EIE) Mission Area Portfolio Management and Mission Decision Packet Management. In order to support multi-domain operations, the Army will have to connect Enterprise networks and tactical networks. —LTG Morrison, DCS, G-6 DCS G-6 released the Army Unified Network Plan under the Army Digital Transformation Strategy, to help the Army to establish a Multi-Domain Operations capable force by 2028. The Unified Network will enable Army formations, as part of the Joint Force, to operate in highly contested and congested operational environments with the speed and global range to achieve decision dominance and maintain overmatch. The plan shapes, synchronizes, integrates and governs Unified Network efforts and aligns the personnel, organizational structure and capabilities required to enable MDO at all echelons. == Chief signal officers and their successors == Chief signal officers (1860–1964) Maj. Albert J. Myer 1860–1863 Lt. Col. William J. L. Nicodemus 1863–1864 Col. Benjamin F. Fisher 1864–1866 Col. Albert J. Myer 1866–1880 (promoted to brigadier general 16 June 1880) Brig. Gen. William B. Hazen 1880–1887 Brig. Gen. Adolphus W. Greely 1887–1906 Brig. Gen. James Allen 1906–1913 Brig. Gen. George P. Scriven 1913–1917 Brig. Gen. George O. Squier 1917–1923 (promoted to major general 6 October 1917) Maj. Gen. Charles McK. Saltzman 1924–1928 Maj. Gen. George Sabin Gibbs 1928–1931 Maj. Gen. Irving J. Carr 1931–1934 Maj. Gen. James B. Allison 1935–1937 Maj. Gen. Joseph O. Mauborgne 1937–1941 Maj. Gen. Dawson Olmstead 1941–1943 Maj. Gen. Harry C. Ingles 1943–1947 Maj. Gen. Spencer B. Akin 1947–1951 Maj. Gen. George I. Back 1951–1955 Lt. Gen. James D. O’Connell 1955–1959 Maj. Gen. Ralph T. Nelson 1959–1962 Maj. Gen. Earle F. Cook 1962–1963 Maj. Gen. David Parker Gibbs 1963–1964 Chiefs of communications-electronics (1964–1967) Maj. Gen. David Parker Gibbs 1964–1966 Maj. Gen. Walter E. Lotz, Jr. 1966–1967 Assistant chiefs of staff for communications-electronics (1967–1974) Maj. Gen. Walter E. Lotz, Jr. 1967–1968 Maj. Gen. George E. Pickett 1968–1972 Lt. Gen. Thomas Rienzi 1972–1974 Directors of telecommunications and command and control (1974–1978) (a directorate of ODCSOPS) Lt. Gen. Thomas Rienzi 1974–1977 Lt. Gen. Charles R. Myer 1977–1978 Assistant chiefs of staff for automation and communications (1978–1981) Lt. Gen. Charles R. Myer 1978–1979 Maj. Gen. Clay T. Buckingham 1979–1981 Assistant deputy chiefs of staff for operations and plans (command, control, communications, and computers) (1981–1984) Maj. Gen. Clay T. Buckingham 1981–1982 Maj. Gen. James M. Rockwell 1982–1984 Assistant chiefs of staff for information management (1984–1987) Lt. Gen. David K. Doyle 1984–1986 Lt. Gen. Thurman D. Rodgers 1986–1987 Directors of information systems for command, control, communications, and computers Lt. Gen. Thurman D. Rodgers 1987–1988 Lt. Gen. Bruce R. Harris 1988–1990 Lt. Gen. Jerome B. Hilmes 1990–1992 Lt. Gen. Peter A. Kind 1992–1994 Lt. Gen. Otto J. Guenther 1995–1997 Lt. Gen. William H. Campbell Chief Information Officer, Military Deputy to the Army Acquisition Executive, and Director of Information Systems for Command, Control, Communications and Computers Lt. Gen. William H. Campbell 1997–2000

Abjjad

Abjjad is an Arabic reading application that was launched in June 2012 by Eman Hylooz. Abjjad offers users the ability to download and read thousands of books offline through its iOS and Android applications. In December of 2020, Abjjad had more than 1.5 million registered accounts. == About Abjjad == Abjjad was founded in June 2012 by Eman Hylooz as a reader community dedicated to Arab readers, authors, and book lovers. Abjjad developed into a smart electronic platform to provide Arabic electronic books with ease to Arab readers everywhere after discovering a large gap in the world of Arab publishing, which is the legal electronic publishing, by forming strategic partnership with Arab publishers such as Dar Al-Shorouk, Dar Al Tanweer, Dar Al Adab, and Dar Al Saqi. == History == In May 2012, Oasis500 provided Abjjad with the seed funding to launch the website. In June 2012, Abjjad was launched with a budget of 15 thousand dollars. Within the first three months more than 10 thousand members were registered in Abjjad. Abjjad has participated in different local and international forums to meet several investors and entrepreneurs. In October 2012 Abjjad participated in Global thinkers forum in Amman, Jordan where Eman Hylooz, founder & CEO, presented the concept of Abjjad, its vision and future plans In mid-December 2012 Abjjad participated in Global Entrepreneurship in Dubai where it was presented to investors as a start-up and a new project in the Middle East. In February 2013 Abjjad was one of ten startups MENA apps has nominated from Jordan and Palestine to participate in startup Turkey. In May 2013 Abjjad participated in World Economic Forum in Amman, Jordan and later in June 2013 participated in Arab Net in Dubai. By the end of 2013, Abjjad won the Mohammed Bin Rashid Al Maktoum's Best Arab Start-Up Business Award for 2013. During 29 October 2013 till January 2014 Abjjad has launched their campaign for crowd funding through Eureeca Abjjad managed to raise US$161,000 in 88 days from 43 regional donors, over US$40,000 over its initial target. By the end of 2020. Abjjad had raised a $1 million investment round led by Jordan Entrepreneurship Fund, Ramal Capital Fund, and JordInvest Fund. Because the funds will be used to acquire users and e-books, Abjjad hopes to become the largest Arab electronic library as well as the largest income-generating platform for Arab authors and publishers, while also providing readers with a unique digital reading experience. == Features == The ability to read an unlimited number of books from an electronic library containing thousands of Arabic and translated books. Abjjad ebook library is constantly expanding and cooperating with new publishing houses to add more books. Reading offline without an internet connection. The application allows the user to download books in seconds and read them anywhere. Intuitive feature which include the ability to flip the pages of the book, highlight the reader's favorite quotes, and add notes, in addition to night reading mode and the option to modify the style and size of the front. The ability to interact with other readers and read their book reviews. More than 1.5 million Arabic readers make up the Abjjad reader community, and the user can read and connect with their reviews, book ratings, and favorite quotes. A virtual personal library that enables the user to rate and organize books by placing them on one of the three shelves: I will read it, currently readings, and/or read it. Abjjad's library includes various genres and literary fields, such as: reference books, novels, stories, literature, psychological books, philosophy, biography, politics, history, religion, self-improvement and human development books, as well as international books translated into Arabic. The library includes the most famous works of Arab authors such as: Naguib Mahfouz, Mahmoud Darwish, Radwa Ashour, Tayeb Salih. Aside from Arabic translation of works by well-known worldwide authors including: Elif Shafak, Fyodor Dostoevsky, Mark Manson, and others. == Statistics == In December of 2020, Abjjad had more than 1.5 million registered accounts. == Awards and honors == 2013: Won the Mohammad Bin Rashid Award for Best Arabic Startup 2014: Won the Golden Award for Jawa's "Best Online Community" 2015: Won the Business Women of the Year Award by Bank al Etihad 2016: Won the Said Khoury Award for Entrepreneurs and Innovators 2016: Won the Best Application in the Arabic Region Award by His Highness Sheikh Salem Al-Ali Al-Sabah in Kuwait. 2019: Won the Mohammad Bin Rashid Award for Arabic Language for the best artistic, cultural or intellectual world to serve the Arabic language. == Abjjad in the media == Abjjad has taken a huge interest in the Middle Eastern and western media; the author of Startup Rising: The Entrepreneurial Revolution Remaking the Middle East, Christopher M. Schroeder, has interviewed Eman Hylooz and wrote about her experience with Abjjad in his book. In addition, France24-Monte Carlo Doualiya has interviewed Ms. Hylooz on Retweet program to discuss Abjjad idea and provide the latest statistics of the website. Moreover, Sky News Arabia interviewed Hylooz to relate her experience with Oasis500 and Eureeca in Abjjad's crowdinvestment campaignPage text. furthermore, Al-Aan TV interviewed Ms.Hylooz in ArabNet in Dubai, 2013. Abjjad has been mentioned on Oasis500 website as one of the five startups which the company funded and gained different prizes. Wamda, Mediame and crowdfundinsider have discussed Abjjad's experience in the crowd investment on Eureeca. And the expert in the Arabic literature in English, M. Lynx Qualey, has interviewed Eman Hylooz in March 2013 to talk about Abjjad's story of success, how it differs from other social networks and what are its future plans. Abjjad was also featured in "Hashtag Arabi" website when it launched its premium subscription called "Abjjad Unlimited" in 2017 with the support of the Abdul Hameed Shoman Foundation. In her interview with the Jordan Times, Eman also discussed her background in computer science and software development, which helped her found Abjjad.